[
	{
		"Unit": "CPU-M-CF",
		"EventCode": "0",
		"EventName": "CPU_CYCLES",
		"BriefDescription": "Cycle Count",
		"PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "1",
		"EventName": "INSTRUCTIONS",
		"BriefDescription": "Instruction Count",
		"PublicDescription": "This counter counts the total number of instructions executed by the CPU."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "2",
		"EventName": "L1I_DIR_WRITES",
		"BriefDescription": "Level-1 I-Cache Directory Write Count",
		"PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "3",
		"EventName": "L1I_PENALTY_CYCLES",
		"BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
		"PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "4",
		"EventName": "L1D_DIR_WRITES",
		"BriefDescription": "Level-1 D-Cache Directory Write Count",
		"PublicDescription": "This counter counts the total number of level-1 data-cache directory writes."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "5",
		"EventName": "L1D_PENALTY_CYCLES",
		"BriefDescription": "Level-1 D-Cache Penalty Cycle Count",
		"PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "32",
		"EventName": "PROBLEM_STATE_CPU_CYCLES",
		"BriefDescription": "Problem-State Cycle Count",
		"PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "33",
		"EventName": "PROBLEM_STATE_INSTRUCTIONS",
		"BriefDescription": "Problem-State Instruction Count",
		"PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "34",
		"EventName": "PROBLEM_STATE_L1I_DIR_WRITES",
		"BriefDescription": "Problem-State Level-1 I-Cache Directory Write Count",
		"PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes while the CPU is in the problem state."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "35",
		"EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES",
		"BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
		"PublicDescription": "This counter counts the total number of penalty cycles for level-1 instruction cache or unified cache while the CPU is in the problem state."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "36",
		"EventName": "PROBLEM_STATE_L1D_DIR_WRITES",
		"BriefDescription": "Problem-State Level-1 D-Cache Directory Write Count",
		"PublicDescription": "This counter counts the total number of level-1 data-cache directory writes while the CPU is in the problem state."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "37",
		"EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES",
		"BriefDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count",
		"PublicDescription": "This counter counts the total number of penalty cycles for level-1 data cache while the CPU is in the problem state."
	}
]
